JEDEC JESD82-15

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This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a CUA878 PLL clock device for registered DDR2 DIMM applications. The purpose is to provide a standard for a CUA878 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Product Details

Published:
11/01/2005
Number of Pages:
21
File Size:
1 file , 170 KB

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