JEDEC JESD 22-A117B

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This method establishes a standard procedure for determining the data cycling endurance and data retention capability of non-volatile memory cells. It is intended as a qualification and monitor test procedure. This test is also applicable to FLASH EEPROM integrated circuits and Erasable Programmable Logic Devices (EPLD) with embedded EEPROM or FLASH memory.

Product Details

Published:
03/01/2009
Number of Pages:
22
File Size:
1 file , 170 KB

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