IEC 62142 Ed. 1.0 en:2005
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- IEC
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Defines a set of modeling rules for writing Verilog® HDL descriptions for synthesis. Adherence to these rules guarantees the interoperability of Verilog HDL descriptions between register-transfer level synthesis tools that comply to this standard. The standard de.nes how the semantics of Verilog HDL are used, for example, to describe level- and edge-sensitive logic. It also describes the syntax of the language with reference to what shall be supported and what shall not be supported for interoperability.
Product Details
- Edition:
- 1.0
- Published:
- 06/27/2005
- Number of Pages:
- 109
- File Size:
- 1 file , 750 KB
