JEDEC JEP120-A

INDEX OF TERMS DEFINED IN JEDEC PUBLICATIONS
standard by JEDEC Solid State Technology Association, 05/01/2000

JEDEC JESD8-6

ADDENDUM No. 6 to JESD8 – HIGH SPEED TRANSCEIVER LOGIC (HSTL)- A 1.5 V OUTPUT BUFFER SUPPLY VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 08/01/1995

JEDEC JESD8C.01

INTERFACE STANDARD FOR NOMINAL 3.0 V/3.3 V SUPPLY DIGITAL INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 09/01/2007

JEDEC JESD209-4-1

Addendum No. 1 to JESD209-4 – Low Power Double Data Rate 4 (LPDDR4)
Amendment by JEDEC Solid State Technology Association, 01/01/2017

JEDEC JESD245B.01

Byte Addressable Energy Backed Interface
standard by JEDEC Solid State Technology Association, 09/01/2017

JEDEC JESD78E

IC LATCH-UP TEST
standard by JEDEC Solid State Technology Association, 04/01/2016

JEDEC JESD47J.01

STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 09/01/2017

JEDEC JESD252

SERIAL FLASH RESET SIGNALING PROTOCOL
standard by JEDEC Solid State Technology Association, 10/01/2018

JEDEC JESD229

Wide I/O Single Data Rate (Wide I/O SDR)
standard by JEDEC Solid State Technology Association, 12/01/2011

JEDEC JEP170

Guidelines for Visual Inspection and Control of Flip Chip Type Components (FCxGA)
standard by JEDEC Solid State Technology Association, 01/01/2013