ADDENDUM No. 6 to JESD8 – HIGH SPEED TRANSCEIVER LOGIC (HSTL)- A 1.5 V OUTPUT BUFFER SUPPLY VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 08/01/1995
INTERFACE STANDARD FOR NOMINAL 3.0 V/3.3 V SUPPLY DIGITAL INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 09/01/2007
MEASURING WHISKER GROWTH ON TIN AND TIN ALLOY SURFACE FINISHES
standard by JEDEC Solid State Technology Association, 07/01/2008
IC LATCH-UP TEST
standard by JEDEC Solid State Technology Association, 04/01/2016
STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 09/01/2017
SERIAL FLASH RESET SIGNALING PROTOCOL
standard by JEDEC Solid State Technology Association, 10/01/2018
Wide I/O Single Data Rate (Wide I/O SDR)
standard by JEDEC Solid State Technology Association, 12/01/2011
Guidelines for Visual Inspection and Control of Flip Chip Type Components (FCxGA)
standard by JEDEC Solid State Technology Association, 01/01/2013
STANDARD FOR DEFINITION OF THE SSTV16859 2.5 V, 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR STACKED DDR DIMM APPLICATIONS
standard by JEDEC Solid State Technology Association, 05/01/2003
CONDITIONS FOR MEASUREMENT OF DIODE STATIC PARAMETERS
standard by JEDEC Solid State Technology Association, 12/01/1992
