JEDEC JESD70

2.5 V BiCMOS LOGIC DEVICE FAMILY SPECIFICATION WITH 5 V TOLERANT INPUTS AND OUTPUTS
standard by JEDEC Solid State Technology Association, 06/01/1999

JEDEC JESD57

TEST PROCEDURE FOR THE MANAGEMENT OF SINGLE-EVENT EFFECTS IN SEMICONDUCTOR DEVICES FROM HEAVY ION IRRADIATION
standard by JEDEC Solid State Technology Association, 12/01/1996

JEDEC JESD22-A119 (R2009)

LOW TEMPERATURE STORAGE LIFE
standard by JEDEC Solid State Technology Association, 11/01/2004

JEDEC JESD79-2F

DDR2 SDRAM SPECIFICATION
standard by JEDEC Solid State Technology Association, 11/01/2009

JEDEC JESD245

Byte Addressable Energy Backed Interface
standard by JEDEC Solid State Technology Association, 12/01/2015

JEDEC JESD 22-A111

EVALUATION PROCEDURE FOR DETERMINING CAPABILITY TO BOTTOM SIDE BOARD ATTACH BY FULL BODY SOLDER IMMERSION OF SMALL SURFACE MOUNT SOLID STATE DEVICES
standard by JEDEC Solid State Technology Association, 05/01/2004

JEDEC JEP155A.01

RECOMMENDED ESD TARGET LEVELS FOR HBM/MM QUALIFICATION
standard by JEDEC Solid State Technology Association, 03/01/2012

JEDEC JESD85

METHODS FOR CALCULATING FAILURE RATES IN UNITS OF FITS
standard by JEDEC Solid State Technology Association, 07/01/2001

JEDEC JEP120-A

INDEX OF TERMS DEFINED IN JEDEC PUBLICATIONS
standard by JEDEC Solid State Technology Association, 05/01/2000

JEDEC JESD8-6

ADDENDUM No. 6 to JESD8 – HIGH SPEED TRANSCEIVER LOGIC (HSTL)- A 1.5 V OUTPUT BUFFER SUPPLY VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 08/01/1995