JEDEC JESD90

A PROCEDURE FOR MEASURING P-CHANNEL MOSFET NEGATIVE BIAS TEMPERATURE INSTABILITIES
standard by JEDEC Solid State Technology Association, 11/01/2004

JEDEC JESD 82-28A

FULLY BUFFERED DIMM DESIGN FOR TEST, DESIGN FOR VALIDATION (DFx)
standard by JEDEC Solid State Technology Association, 07/01/2008

JEDEC JESD 82-27

DEFINITION OF THE SSTUB32869 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS
standard by JEDEC Solid State Technology Association, 05/01/2007

JEDEC JESD22-B103B (R2010)

VIBRATION, VARIABLE FREQUENCY
standard by JEDEC Solid State Technology Association, 06/01/2002

JEDEC JEP166A

JC-42.6 MANUFACTURER IDENTIFICATION (ID) CODE FOR LOW POWER MEMORIES
standard by JEDEC Solid State Technology Association, 12/01/2014

JEDEC JESD51-11

TEST BOARDS FOR THROUGH-HOLE AREA ARRAY LEADED PACKAGE THERMAL MEASUREMENT
standard by JEDEC Solid State Technology Association, 06/01/2001

JEDEC JESD46D

CUSTOMER NOTIFICATION OF PRODUCT/PROCESS CHANGES BY ELECTRONIC PRODUCT SUPPLIERS
standard by JEDEC Solid State Technology Association,

JEDEC JESD12

SEMICUSTOM INTEGRATED CIRCUITS (FORMERLY PUBLISHED AS STANDARD FOR GATE ARRAY BENCHMARK SET)
standard by JEDEC Solid State Technology Association, 06/01/1985

JEDEC JESD 46C

CUSTOMER NOTIFICATION OF PRODUCT/PROCESS CHANGES BY SEMICONDUCTOR SUPPLIERS
standard by JEDEC Solid State Technology Association, 10/01/2006

JEDEC JESD 209-2B

LOW POWER DOUBLE DATA RATE 2 (LPDDR2)
standard by JEDEC Solid State Technology Association, 02/01/2010