JEDEC JEP110
GUIDELINES FOR THE MEASUREMENT OF THERMAL RESISTANCE OF GaAs FETS
standard by JEDEC Solid State Technology Association, 07/01/1988
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GUIDELINES FOR THE MEASUREMENT OF THERMAL RESISTANCE OF GaAs FETS
standard by JEDEC Solid State Technology Association, 07/01/1988
ELECTRICALLY ERASABLE PROGRAMMABLE ROM (EEPROM) PROGRAM/ERASE ENDURANCE AND DATA RETENTION TEST
standard by JEDEC Solid State Technology Association, 03/01/2009
LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD FOR LEADED SURFACE MOUNT PACKAGES
standard by JEDEC Solid State Technology Association, 08/01/1996
WIDE I/O 2 (WideIO2)
standard by JEDEC Solid State Technology Association, 08/01/2014
GUIDELINE FOR RESIDUAL GAS ANALYSIS (RGA) FOR MICROELECTRONIC PACKAGES
standard by JEDEC Solid State Technology Association, 07/01/2002
STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 08/01/2017
MARKING AND LABELING OF COMPONENTS, PCBs AND PCBAs TO IDENTIFY LEAD (Pb), Pb-FREE AND OTHER ATTRIBUTES
standard by JEDEC Solid State Technology Association, 05/01/2007
TRANSISTOR, GALLIUM ARSENIDE POWER FET, GENERIC SPECIFICATION
standard by JEDEC Solid State Technology Association, 07/01/1992
POD10 – 1.0 V Pseudo Open Drain Interface
standard by JEDEC Solid State Technology Association, 09/01/2011
STANDARD FOR DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE BiCMOS LOGIC DEVICES
standard by JEDEC Solid State Technology Association, 05/01/1996