1.2 V +/- 0.1 V (NORMAL RANGE) AND 0.8 – 1.3 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 09/01/2007
COMMON FLASH INTERFACE (CFI) IDENTIFICATION CODES
standard by JEDEC Solid State Technology Association, 05/01/2004
HYBRIDS/MCM
standard by JEDEC Solid State Technology Association, 09/01/2005
UNIFIED WIDE POWER SUPPLY VOLTAGE RANGE CMOS DC INTERFACE STANDARD FOR NON-TERMINATED DIGITAL INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 10/01/2009
EXTERNAL VISUAL
standard by JEDEC Solid State Technology Association, 08/01/2009
Lognormal Analysis of Uncensored Data, and of Singly Right-Censored Data Utilizing the Persson and Rootzen Method
standard by JEDEC Solid State Technology Association, 08/01/2017
TEST METHOD FOR BEAM ACCELERATED SOFT ERROR RATE
standard by JEDEC Solid State Technology Association, 11/01/2007
SOLDER BALL SHEAR
standard by JEDEC Solid State Technology Association, 10/01/2006
STANDARD FOR DESCRIPTION OF FAST CMOS TTL COMPATIBLE LOGIC
standard by JEDEC Solid State Technology Association, 01/01/1993
ADDENDUM No. 1 to JESD12 – TERMS AND DEFINITIONS FOR GATE ARRAYS AND CELL-BASED INTEGRATED CIRCUITS
Amendment by JEDEC Solid State Technology Association, 08/01/1993
