JEDEC JESD51-10

TEST BOARDS FOR THROUGH-HOLE PERIMETER LEADED PACKAGE THERMAL MEASUREMENTS
standard by JEDEC Solid State Technology Association, 07/01/2000

JEDEC JEP 122E

FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICES
standard by JEDEC Solid State Technology Association, 03/01/2009

JEDEC JESD8-5A.01

ADDENDUM No. 5 to JESD8 – 2.5 V 0.2 V (NORMAL RANGE), AND 1.8 V TO 2.7 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUIT
standard by JEDEC Solid State Technology Association, 09/01/2007

JEDEC JESD51-31

THERMAL TEST ENVIRONMENT MODIFICATIONS FOR MULTICHIP PACKAGES
standard by JEDEC Solid State Technology Association, 07/01/2008

JEDEC JESD 22-A110C

HIGHLY ACCELERATED TEMPERATURE AND HUMIDITY STRESS TEST (HAST)
standard by JEDEC Solid State Technology Association, 01/01/2009

JEDEC JEP122G

FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICES
standard by JEDEC Solid State Technology Association, 10/01/2011

JEDEC JESD76

DESCRIPTION OF 1.8 V CMOS LOGIC DEVICES
standard by JEDEC Solid State Technology Association, 04/01/2000

JEDEC JESD 218

SOLID STATE DRIVE (SSD) REQUIREMENTS AND ENDURANCE TEST METHOD
standard by JEDEC Solid State Technology Association, 09/01/2010

JEDEC JEP121A

REQUIREMENTS FOR MICROELECTRONIC SCREENING AND TEST OPTIMIZATION
standard by JEDEC Solid State Technology Association, 10/01/2006

JEDEC JEP159A

PROCEDURE FOR THE EVQLUQTION OF LOW-k/METAL INTER/INTRA-LEVEL DIELECTRIC INTEGRITY
standard by JEDEC Solid State Technology Association, 07/01/2015