JEDEC JESD8-15A
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- JEDEC
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This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the SSTL_18 logic switching range, nominally 0 V to 1.8 V. The standard may be applied to ICs operating with separate VDD and VDDQ supply voltages. The VDD value is not specified in this standard; however VDD and VDDQ will have the same voltage level in many cases.
Product Details
- Published:
- 09/01/2003
- Number of Pages:
- 21
- File Size:
- 1 file , 290 KB