JEDEC JESD82-21
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- JEDEC
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This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a CUA845 PLL clock device for registered DDR2 DIMM applications.The purpose is to provide a standard for a CUA845 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.
Product Details
- Published:
- 01/01/2007
- Number of Pages:
- 20
- File Size:
- 1 file , 170 KB
